According to the latest report, devised from leaked AMD software patch, AMD's upcoming Zen architecture could offer significant core increase in per-core performance due to the double the number of decoder, ALU and floating-point units per-core.

According to a latest report from 3DCenter.org, which shows an AMD Zen block diagram which was made from details from the latest AMD software, the AMD Zen CPU could end up with four instruction decoders, four Integer units (ALUs), two address units (AGUs) and four 128-bit wide floating-point units combined in two 256-bit FMACs.

When compared to previous and current Bulldozer and Steamroller CPU architectures, which used a module design, the Zen architecture uses one integer cluster in a single Zen core. The Zen architecture will end up with two times the amount of execution units and four times more floating-point units as well as simultaneous multi-threading (SMT) technology which is quite similar to Intel's Hyper-Threading. Unfortunately, we still do not have any details regarding cache size but it is believed that AMD Zen CPU could run between 3.5 and 4.0GHz.

According to earlier rumors, FX-series CPUs based on Zen architecture are expected to come out sometime in 2016, together with the new AM4 socket while mainstream APUs and server parts should follow in 2017.





Source: 3DCenter.org.