While we already wrote a bit about AMD's upcoming Zen CPU architecture we now get to check out the core block diagram, which details the earlier mentioned monolithic core design as well as shed more details regarding the architecture.

While we already knew that AMD's Zen architecture will move away from a multi-core module design seen with Bulldozer architecture, the core block diagram shows more details regarding monolithic fetch and decode units.

While Bulldozer had two cores per module with dedicated decode and integer units with shared floating-point scheduler, the Zen architecture features a single decode unit with single integer and floating-point schedule. The single integer unit has six pipelines, compared to four per core on Bulldozer architecture.

That same floating-point scheduler is connected to two 256-bit FMAC units, which will most likely be fused to process 512-bit AVX floating point instructions, which is significant push from two 128-bit FMAC units with the Bulldozer architecture.

The Zen core also comes with dedicated 512KB of L2 cache, which although sounds quite less than shared 2MB of cache per module on the Bulldozer architecture, might suggest that Zen core is able to get more throughput without the need of a large cache.

While we still do not have all the details, AMD's Zen architecture looks like a good way forward and hopefully it will bring AMD back on track when it comes to CPU market.



Source: Wccftech.com.