Tegra 3 - Design Perspective

Published by Marc Büchel on 13.12.11
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Less Leakage Power

At this point NVIDIA had several opportunities. One was for example that they could stick with the Tegra 2 design and optimize it for lower leakage power. Another more radical approach would have been to use TSMCs LP manufacturing process. But this would have thrown back the company from a performance perspective. Instead they headed for a much more creative way. What they did is to create a five core SoC whereas the fifth core is called the companion core. This companinon core is made using the TSMCs LP process which means that there will be very low leakage powers. This processor takes over when a Tegra 3 device is locked for example, so all the background processes will run with on a core that uses way less power. Furhtermore NVIDIA integrated power gating. This means that the core logic can be deactivated. Core which are not needed will therefore be shut down and drain no power at all. Like this NVIDIA elegantly solved the problem with the leakage power and as a consequence there could now even be smartphones based on NVIDIAs Tegra 3 SoC.

A look at other parts of the SoC reveals that Tegra 3 also went through some evolution processes. The new SoC for example features NEON-Support which is being realized via a ARM MPE (Media Processing Engine). To keep the Tegra 2 die as compact as possible NVIDIA decided to not support NEON with Tegra 2. Actually NEON is an instruction set which allows 2D as well as 3D acceleration. Furthermore it can also accelerate sound synthesis.



If we also take a closer look at the GPU we don't see a lot of differences. There is also more evolution than revolution. Whereas Tegra 2 had vier pixel and four vertex shaders, Tegra 3 now has twice as many shader units but still the same amount of vertex processors. The core count went up to twelve.


Page 1 - Introduction
Page 2 - Less Leakage Power
Page 3 - Cache Hierarchie and Clock Speeds
Page 4 - Is it the right way to go?


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