Results

9-10-9-27-2T - Timings

As we can see on the chart at CL9-10-9-27-2T the modules perform best when provided with 1.55 Volt. With this voltage they were capable of running 1'154 MHz. Unfortunately at this point we hit the BCLK wall of our Sandy Bridge test setup. Therefore it simply wasn't possible to increase the BLCK any higher than 108.1. We're under the impression that these modules could cope with even higher frequencies, but the CPUs memory controller is limiting.

7-10-7-27-1T - Timings

With CL7-10-7-27 and 1.7 VDIMM we were able to reach a maximum clock speed of 1'154 MHz. Lowering the latencies will result in a significant growth in performance regarding raw throughput. We also see that this test confirms our statement before where we said that these modules still have potential. Even with these low latencies it was possible to hit the BCLK wall again. Therefore it simply wasn't possible to run more than 108.1 MHz BLCK.

Page 1 - Introduction	Page 4 - Test Setup
Page 2 - Preview	Page 5 - Results
Page 3 - Technical Details	Page 6 - Conclusion

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