It appears that SuperComputing 15 conference in Austin was quite interesting as Intel certainly pushed hard with its upcoming Knights Landing Xeon Phi chip showing both the wafer as well as the chip, in both processor and PCIe add-in co-processor versions.

While the previous Knights Corner Xeon Phi chip was available as a PCI-Express co-processor and with 6GB, 8GB and 16GB of on-board memory, the Knights Landing Xeon Phi chip is a bit different as it features up to 16GB of on-board high-bandwidth MCDRAM memory from Micron, in addition to 6-channel DDR4 memory controller, up to 36 PCIe gen3 lanes and Intel Omni-Path.

The wafer, pictured by Anandtech.com, includes 9.4 dies horizontally and 14 dies vertically, suggesting that Knights Landing (KNL) is one big chip with a die size of around 31.9x21.4mm or around 683mm2. This also means that it packs between 10.4 and 11.7 million transistors per square millimeter.

What makes the Knights Landing Xeon Phi chip interesting is that it will also be available as a PCIe add-in coprocessor card as well as as the main processor, unlike the Knights Corner which was only available as a PCIe add-in coprocessor. By putting the Knights Landing in a socket will give it access to both 16BG of MCDRAM memory as well as access to six memory channels with support for up to 384GB of DDR4 memory.

As you can see on the picture from Anandtech.com, there is a significant difference between the processor and co-processor versions, which uses an internal connecotr for both data and Omni-Path connection. The connector aet the end of the co-processor has an additional chip which is most likely an Intel Omni-Path connector that will go into a PCIe card.

Anandtech.com also caught a picture of Intel's reference motherboard with six-channel DDR4 support, allowing to be placed in a 1U blade server.

As unveiled earlier, Intel's Knights Landing Xeon Phi should be available in Q1 2016.







Source: Anandtech.com.